Sub-micron multi-level metallization is one of the key technologies for ultra large scale integration (ULSI). The multilevel interconnects that lie at the heart of this technology require planarization of interconnect features formed in high aspect ratio openings, including contacts, vias, metal interconnect lines and other features. Reliable formation of these interconnect features is very important to the success of ULSI and to the continued effort to increase circuit density and quality on individual substrates and die.
Copper and copper alloys have become the metal of choice for filling sub-micron, high aspect ratio interconnect features on semiconductor substrates. Copper and its alloys have lower resistivity compared to other metals such as, for example, aluminum. These characteristics are critical for achieving higher current densities with increased device speed. Copper, however, has exhibited certain processing problems that must be overcome to achieve a mature copper metal interconnect semiconductor processing technology. For example, copper filled features have been found to have a tendency to form sharp protrusions, otherwise known as hillocks into overlying material layers, for example a nitride layer formed to contact the copper and while subjected to thermal processing temperatures. The cause of the formation of copper hillocks has been thought to be related to thermal mismatch stresses as well as low electromigration resistance and the low strength and ductility of copper which may contribute to the formation of hillocks in a subsequent plasma enhanced and thermal processes.
Other problems associated with copper filled semiconductor features include the fact that copper, for example, electro-chemically deposited copper tends to form relatively large grains in subsequent thermal processes which increases the roughness of surface morphology thereby compromising adhesion of overlying layers. In addition, the tendency of copper to form copper oxides at exposed surfaces at room temperature in the presence of oxygen containing atmospheres presents processing constraints to prevent formation of copper oxides at the surface and penetrating into the copper bulk via grain boundary diffusion. The formation of copper oxides at the copper surface within grain boundaries degrades the overall resistivity of the copper feature and contributes to other reliability problems including reducing adhesion of overlying material layers in contact with the copper feature.
One exemplary process for forming a series of interconnected multiple layers, for example, is a damascene process. Although there are several different manufacturing methods for manufacturing damascene structures, all such methods employ at least two photolithographic masking and etching steps, typically including a reactive ion etch (RIE). In the typical multilayer semiconductor manufacturing process, for example, a series insulating layers are deposited to include a series of interconnecting metallization structures such as vias and trench lines to electrically interconnect different device levels (e.g., vias) and to interconnect various areas within a device level (e.g., trench lines). In most devices, pluralities of vias are separated from one another along a process wafer and selectively interconnect conductive regions between layers of a multi-layer device. Trench lines typically serve to selectively interconnect conductive regions within a layer of a multilayer device. Vias and trench lines formed together, for example a trench line overlying one or more vias is referred to as a dual damascene.
For example, in a typical dual damascene process, an opening is formed by at least two conventional reactive ion etching (RIE) process to first form a via opening in one or more dielectric insulating layers followed by a similar process to form a trench line opening overlying and encompassing one or more via openings to form a dual damascene opening. Prior to filling the dual damascene opening with a metal, for example copper, a barrier layer is deposited to cover the sidewalls and bottom portion of the feature opening to prevent copper diffusion into the dielectric insulating layer and to improve the adhesion of an overlying copper layer filling the feature opening. For example, an electrochemical deposition (ECD) method also known as electroplating is used to deposit copper since it is a preferable method to achieve superior step coverage in sub-micron feature openings. The method generally includes depositing a metal seed layer, for example copper, over the barrier layer and then electroplating copper over the seed layer to fill a feature opening to form a dual damascene structure. A seed layer is required to carry electrical current for electroplating, the seed layer preferably being continuous over the wafer surface to provide for uniform electro-deposition of copper. The deposited copper layer is then planarized, for example by chemical mechanical polishing (CMP), to define a conductive interconnect feature. Since copper is easily oxidized when exposed to moisture or oxygen containing ambient, typically a protective layer is formed soon after the CMP process defining the copper filled feature.
To overcome the several processing challenges associated with copper technology, prior art processes have proposed depositing a copper alloy seed layer including various metal additives to form a copper alloy over the barrier layer to improve adhesion and electromigration resistance of the copper filled feature. For example, U.S. Pat. No. 6,181,012 proposes forming a copper alloy seed layer prior to forming an overlying copper layer to improve adhesion and electromigration resistance of the overlying copper layer. U.S. Pat. Nos. 5,243,222 and 5,130,274 teach the formation of copper alloys for diffusion barriers. However, none of these processes teach methods of copper feature formation that adequately address problems related to the bulk properties of the copper filled feature including the formation of copper hillocks penetrating into material layers overlying the copper feature. In addition, the prior art processes do not address bulk properties of the copper feature including bulk electromigration, grain boundary oxidation, and adhesion of material layers formed overlying the copper feature. Moreover, prior art processes significantly increase the resistivity of the copper feature making such processes unacceptable for 0.13 micron technologies and below.
These and other shortcomings demonstrate a need in the semiconductor device processing art to develop a method for forming copper filled features with more robust bulk properties including among other properties, resistance to bulk copper electromigration and stress migration, improved adhesion of material layers to the copper feature, and resistance to grain boundary oxidation.
It is therefore an object of the invention to provide a method for forming copper filled features with more robust bulk properties including among other properties, resistance to bulk copper electromigration and stress migration, improved adhesion of material layers to the copper feature, and resistance to grain boundary oxidation while overcoming other shortcomings and deficiencies of the prior art.